Date: 27/04/2025

Synopsys and TSMC collaborate on advanced EDA flows for Angstrom-scale designs with A16 and N2P processes

Synopsys and TSMC are working together to provide electronic design automation (EDA) and intellectual property (IP) solutions for TSMC’s advanced process nodes and packaging technologies, supporting AI chip design and 3D multi-die systems. Their collaboration includes certified digital and analog design flows for TSMC’s A16 and N2P processes, enabled by Synopsys.ai, with initial EDA flow development for the A14 process underway. They are also certifying tools for TSMC’s N3C technology, building on existing N3P solutions.

The Synopsys 3DIC Compiler, certified for TSMC’s CoWoS technology, supports 3Dblox and handles 5.5x-reticle interposer sizes for high-density 3D stacking. This enables high-performance computing (HPC) and AI chips with wafer-on-wafer and chip-on-wafer packaging. The compiler provides a unified environment for feasibility studies, prototyping, floorplanning, and high-throughput routing, integrating multi-physics analysis for power, thermal, and signal integrity with Ansys simulation technologies.

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