Date: 01/06/2023

UltraRISC Selects Valtrix STING for Verification of RISC-V SoC

UltraRISC has licensed Valtrix' STING for the design verification of its RISC-V SoC implementations.

STING, a software-driven test stimulus generator from Valtrix, is capable of creating self-checking and architecturally correct portable programs that can be enabled on simulations, emulation, FPGA and silicon.

UltraRISC's Executive President and CTO, Dr. Jiang Jiang said, "Our company conducts rigorous verification to ensure that our processors are well designed and thoroughly verified. Valtrix's STING tool has made a significant contribution to our verification efforts on the UltraRISC's UR-A1 processor core, particularly the hypervisor extension for hardware virtualization. The capability of running tests across simulation and emulations makes it an ideal choice for our DV strategy."

"We are very excited to collaborate with UltraRISC as a lead partner for enabling STING for SoC verification of their advanced RISC-V implementations on hardware emulation platforms," said Shubhodeep Roy Choudhury, CEO of Valtrix. "Complementing the cycles run on simulation with testing on emulation, FPGA and post-silicon is critical in ensuring that the CPU and SoC designs are compliant and free of functional errors. STING's portable stimulus generation capability allows users to run the tests in any device-under-test environment, thus increasing verification reuse and efficiency," he added.

For more information on Valtrix's design verification technology and products, visit: https://www.valtrix.in