Date: 16/05/2023

Alchip Technologies Announces 3DFabric Alliance Support

Alchip Technologies announced its support plans as a founding member of TSMC’s OIP 3DFabric Alliance by using the TSMC 3nm process technology and advanced packaging capabilities.

The company supports the foundry initiative, announced in late October 2022, seeing it as a market driver to enable customers’ leading-edge applications with Alchip’s most advanced high-performance computing ASIC technology.

TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer’s innovation in system level approach. It consists of frontend technologies for 3D silicon stacking, or TSMC-SoIC (System on Integrated Chips), dedicated fabs for 3D stacked dies’ assembling and testing, as well as backend technologies that include CoWoS and InFO family of packaging technologies.

The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform (OIP) and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3D IC ecosystem innovation and readiness. The new alliance partners have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers early availability to the highest-quality, readily-available solutions and services from the partners in EDA, IP, design service, memory, outsourced semiconductor assembly and test (OSAT), substrate, and testing.

“As a high-performance computing ASIC leader, Alchip’s participation in the TSMC 3DFabric Alliance is an imperative,” said Johnny Shen, president and CEO of Alchip Technologies. “This Alliance solidifies TSMC’s semiconductor leadership by providing strategic opportunities for leading-edge, high-performance ASIC companies to extend their most advanced packaging capabilities to innovative technology customers.”

Alchip has been taking 3nm ASIC designs and taped out its first test chip in January 2023. This test chip integrated multiple silicon interposers on package substrate. Each interposer carried multiple chiplets that enabled high-speed die-to-die interconnect between multiple dies to be completely tested. While designing this test chip, Alchip developed a new 3DFabric design flow that can efficiently complete high-speed signal interconnect and power distribution network across multiple dies. By following the design guideline and verification flow defined by Alchip, a customer is assured that signal integrity, power integrity and thermal dissipation design in every 3DFabric project reach the highest safety.

On the advanced packaging front, Alchip has made heavy R&D investments to support TSMC’s 3DFabric technologies with an efficient design flow. The company also plans to generate reference designs with various 3DFabric technologies that help customers evaluate a 3D stacking strategy at early stage of product development. Leveraging the close technology collaboration between TSMC and Alchip, companies exercise significant freedom to design their product with the most advanced 3D packaging technology.

News Source :Alchip