Date: 09/05/2023

Aldec and Thales to Co-Present at Certification Together International Conference 2023

Aldec, Inc. - Together with EASA, FAA, Airbus and other leading avionics regulatory experts and system suppliers, Aldec and Thales will be co-presenting at the Certification Together International Conference (CTIC) to be held in Toulouse, France from May 10-12, 2023.

The CTIC is dedicated to addressing system, software and hardware certification challenges for avionics systems. This year, Aldec and Thales will co-present a technical case study on the use of transaction-level modeling (TLM) for FPGA designs that use high-speed interfaces such as PCIe and Ethernet.

Technical Case Study: Industry’s First use of TLM for the Verification of a PCIe-based FPGA Design for DO-254 Compliance

May 12, 2023, Hardware Track
Presenters: Janusz Kitel, Aldec and Yann Le Hennaf, Thales

The use of high-speed interfaces like PCIe and Ethernet is becoming popular in FPGAs and SoC FPGAs within avionics systems. However, verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with multiple high-speed serial interfaces produce non-deterministic results during physical tests. Simulation results are optimized because they are based on simplified models, while the test results in physical hardware depend on the phases of clock oscillators.

In this presentation, we will discuss the limitations of bit-level verification and introduce TLM, and how it can be used for verifying FPGA designs with high-speed interfaces for DO-254 compliance. Transactions are easier to manage, analyze, and debug. Additionally, the untimed testbenches used with TLM are not sensitive to clock frequency and phase changes, which is ideal for verifying such designs with non-deterministic behavior.

Until now, TLM has not been used to verify a PCIe-based FPGA design requiring DO-254 compliance. This case study recounts an industry first.

Aldec continues to be active in the avionics community helping suppliers and airframers improve and innovate their verification processes with industry-proven tools and solutions. Aldec provides FPGA design/verification tools for DO-254 compliance including:

Requirements Traceability
HDL Coding Standards, Design Rule Checking and Clock Domain Crossing Analysis
DO-254 Templates and Review Checklists
VHDL/Verilog/SystemC Simulation with Code Coverage and UVM Support
Target FPGA At-Speed Device Testing Platform
Tool Qualification Data Packages
3-Day DO-254 Practitioner’s Training

News Source: Aldec