Date: 17/10/2012

Foundry-first Reference Flows from TSMC supporting 20nm and CoWoS

TSMC has announced that the readiness of 20nm and CoWoS design support within the Open Innovation Platform (OIP) is showed by the delivery of two foundry-first Reference Flows supporting 20nm and CoWoS (Chip on Wafer on Substrate) technologies.

TSMC’s 20nm reference flow allows double patterning technology (DPT) design using proven design flows. Leading EDA vendors’ tools are qualified to work with TSMC 20nm process technology by integrating DPT aware place and route, timing, physical verification and design for manufacturing (DFM). The new silicon-validated CoWoS reference flow that permits multi-die integration to support high bandwidth, low power can deliver fast time–to- market for 3D IC designs. The CoWoS flow also helps designers by permitting them to use existing, mainstream tools from leading EDA vendors.

“These Reference Flows give designers access to TSMC’s advanced 20nm and CoWoS technologies,” said TSMC Vice President of R&D, Dr. Cliff Hou. “Delivering advanced silicon and manufacturing technologies as early and completely as possible to our customers is a chief goal for TSMC and its OIP design ecosystem partners.”

20nm Reference Flow:
TSMC’s 20nm reference flow allows 20nm design with DPT aware capabilities to decrease design complexity and deliver required accuracy. DPT enablement consists of pre-coloring capability, new RC extraction methodology, DPT sign-off, physical verification and DFM. In addition, TSMC and its ecosystem partners design 20nm IP for DPT compliance to speed up 20nm process adoption.

CoWoS Reference Flow:
The CoWoS reference flow permits 3D IC multi-die integration. The new CoWoS reference flow enables a smooth transition to 3D IC with minimal changes in existing methodologies. It includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

Custom design reference flow and RF reference design kit:
The custom design reference flow allows DPT in 20nm custom layouts. It offers solutions to 20nm process requirements, including a direct link with simulators for the verification of voltage-dependent DRC rules, and integrated LDE solutions and handling of HKMG technology. RF Reference Design Kit enables new high frequency design guidelines. These consist of 60GHz RF model support, high performance Electromagnetic (EM) characterization that provides customer design capability through the examples of 60GHz front-to-back implementation flow and Integrated Passive Device (IPD) support.

For more information: http://www.tsmc.com

Source: TSMC