Date: 06/09/2012

'hybrid metrology' by NIST to measure nm dimensions in a semiconductor device

NIST has developed 'hybrid metrology' which is combination of scanning techniques and statistical analysis to measure dimension of nanoscale devices in a semiconductor device. NIST created a library of simulated data base on typical chip feature dimensions to which they can compare their actual measurements, made with AFM, scatterometry and other means. A complex statistical analysis of library values is then compared with actual measurements to extract valid measurement values—but this is often at a cost of high uncertainty.

But NIST statistician Nien Fan Zhang found an elegant way to use a statistical method called Bayesian analysis to incorporate a few key additional measured values from other tools into the library model before performing the comparison. In doing so, the team was able to reduce the uncertainty in some of the measurements, lowering them by more than a factor of three in some cases. This approach is expected to be essential when measuring complex three-dimensional transistors 16 nanometers in size or smaller in the near future.

The math wizardry is a little counter-intuitive. "In essence, if you've got a really small uncertainty in your AFM measurement but a big one in your optical measurements, the final uncertainty will end up even smaller than either of them," says NIST scientist Richard Silver. "IBM and GLOBALFOUNDRIES have already begun developing the technique since we first described it at a 2009 conference, and they are improving their measurements using this hybrid approach."