Date: 20/06/2012

Smart card chip platform TESIC from Tiempo silicon proven on TSMC 130nm LP

France based ID-semiconductor device tech expert Tiempo has announced silicon validation of its smartcard and id specific secure platform TESIC manufactured on TSMC 130 nm LP process.

Tiempo says as already observed with its previous clockless circuits, all chip samples were fully functional and matching the expected performance. Tiempo claims this successful circuit is another first-time-right design made with Tiempo unique ACC synthesis tool.

Tiempo describes its TESIC is a complete secure platform for the design of integrated circuits implementing secured transactions such as smartcard chips for banking and ticketing, chips for ePassports or NFC secure elements. The TESIC secure platform leverages Tiempo's unique power/performance auto-scaling and tamper-resistant asynchronous technology delivering unprecedented benefits for demanding embedded security applications, explains Tiempo.

The prototype chips enable Tiempo to confirm the high performances of the TESIC platform for
contactless applications. “This is a very important milestone”, says Serge Maginot, CEO of Tiempo. “Our clockless design flow having a proven maturity and our TESIC platform being silicon-proven, we are now able to offer a complete chip solution with unmatched performance for secured contactless payment applications.”

More at www.tiempo-ic.com.