Date: 18/06/2012

imec demo higher-k dielectric with replacement metal gate transistors at VLSI Sympo

imec has said it has successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200x-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric. The reseach results were presented at the VLSI Technology Symposium this week in Honolulu, Hawaii, USA (June 12-15, 2012).

Imec explains: As 3-D transistors like FinFETs are scaled aggressively into 14nm and beyond, many transistor features approach scales of 10s-100s of atoms. The high-aspect ratio and complex topography of FinFETs, make physical analysis and metrology very challenging. Imec’s advanced physical analysis laboratory performs very active research on next-generation physical analysis and metrology. Imec was able to apply a novel atom probe tomography technique that enables atomic-level resolution of dopant distribution in nanometer-size FinFET. With clear correlation to transistor electrical performance, the new technique provided unprecedented insights into ultra-shallow junction formation in FinFETs, enabling device design and a clearer understanding of how dopant atoms are incorporated in nanometer-scale device volumes.

imec has also highlighted record pMOS performance by SiGe quantum well devices, the potential tech for replacing strained-Si technology.

Aaron Thean, director of imec's logic device program stated: “We are excited by these excellent results of our advanced transistor program Working closely with our technology partners, this work represents some of the focused imec activities to extend Moore’s Law and CMOS technologies. We would also like to thank the VLSI Technology Symposium Committee for their appreciation of our work.”

To know more visit www.imec.be