Date: 30/05/2012

DFI 3.1 supported by Cadence IP, includes LPDDR3 mobile memory

Cadence Design Systems, Inc. has announced that the company's suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1. The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY's low-power interface and training features. The DFI interface standard was developed through the collaborative effort of leaders in the semiconductor and EDA markets and has become the de facto industry standard for high-bandwidth memory interfaces.

"As the performance of the processors used in today's consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs," said Marc Greenberg, director of marketing, SoC Realization, Cadence. "Through our close working relationship with the DFI Group, we are able to offer our customers design and verification IP that supports the latest version of this popular interface standard."

Cadence's DDR3 designs currently in development use the DFI interface. With the addition of support for LPDDR3 memory, the DFI standard can now be used in the development of SoCs targeting smartphone and tablet applications that require higher-bandwidth memory. The standard has been recognized by JEDEC.

DFI 3.1 is a memory interface standard the enables the interoperability of IP between different companies. It defines methods for interfacing to DDR4 devices (with data rates up to 3.2 Gbits/second per pin) and LPDDR3 devices (with data rates up 6.4 Gbits/sec. and 12.8 Gbits/second for a dual channel configuration). The preliminary specification is at www.ddr-phy.org