Date: 13/05/2012

Majority of engineers use VHDL, though SystemVerilog use grows, as per a survey

Aldec Europe has find in its survey, despite the excitement around SystemVerilog within the industry and the increasing popularity of advanced verification methodologies such as UVM, a significant portion of designers intend to stick with VHDL; for a variety of technical, logistical and financial reasons.

John Aynsley, CTO of Doulos says "We're increasingly encountering designers, working in VHDL, that are dealing with bigger and bigger designs. They appreciate the benefits of migrating to SystemVerilog but for some it's too big a leap to make."

Aldec says despite the common perception that VHDL is a dated language that lacks a number of advanced OOP concepts, it appears VHDL users still perform many of the same tasks as SystemVerilog users. For instance, they are able to: use constrained-random verification techniques, develop in-house verification methodologies, track verification plans, analyse verification trends, rank tests, analyse assertion and coverage reports, and use computing grids.

Aynsley adds: "There is undoubtedly a continued need for VHDL support, particularly in Europe as a geographic region and in some specialist industries such as aerospace. Yes, SystemVerilog is growing in popularity - but in terms of engineers signing up for our training courses worldwide it is only recently that we've seen SystemVerilog overtake VHDL. The VHDL language needs to be supported, by vendors and training companies alike, plus initiatives like the recently announced Open-Source VHDL Verification Methodology should be praised for giving the language new momentum."

Of the 2,400+ VLSI design engineers surveyed, 53% indicated they would be using VHDL (in isolation or in combination with another language). The other languages scored: Verilog (31%), SystemVerilog (32%), SystemC (11%), and C/C++ (23%); noting that the multiple-choice aspect means the total is more than 100%.

With regards to verification, 41% do not follow any particular methodology, 45% employ an in-house developed methodology and the remaining respondents rely on SystemVerilog-based OVM/UVM (17%) and VMM (7%). Again, respondents could make multiple choices, so the total is more than 100%.

Dave Rinehart, Vice President of Aldec Inc., notes: "Aldec is first and foremost a verification company, and because our EDA tools have mixed-language capability we're of the opinion our annual verification surveys are unbiased. Also, it's great to see our survey results aligning with what others are seeing in the industry too. VHDL is alive and well."