Date: 09/05/2012

Talk on digital analog design presented by Stanford's Mark Horowitz during DAC

Mark Horowitz, chairman of Stanford University's electrical engineering department, is providing a look at Digital Analog Design during the 49th Design Automation Conference (DAC), as part of the IEEE Council on Electronic Design Automation (CEDA) distinguished speaker series.

The talk is to be held during lunch Tuesday, June 5, from 11:45 a.m.-1:30 p.m. in Room #303 at the Moscone Center in San Francisco. It is open to all DAC attendees on a first-come, first-served basis.

In his talk, Professor Horowitz will describe the advances in digital design tools over the last 30 years, contrasting the more modest progress in analog tools. He will illustrate digital tools' use of abstractions to allow them to validate that implementations match functional models and that the composition of cells matches the composition of the functional models.

Professor Horowitz will explain why this is more difficult for analog circuits and outline how it can be done by illustrating ways to formally validate analog models, define analog fault models, and efficiently explore the effect of process variations.

Professor Horowitz's talk is organized by Joel Phillips of Cadence Design Systems and technical activities chair for CEDA. To learn more about CEDA and its distinguished speaker series or details, go to: http://www.c-eda.org