Date: 09/05/2012

Verific's parser platform adopted by Excellicon for timing constraints solutions

Excellicon has adopted Verific Design Automation's IEEE compliant front-end platform for use with its software for timing constraints authoring, verification and management.

Verific's SystemVerilog and VHDL parsers and register transfer level (RTL) elaborator have been tightly integrated with Excellicon's timing constraints compiler. Excellicon's products are targeted at solving complexity associated with latest requirements in timing constraints, including multi-mode constraints generation, verification and management, as well as full mode analysis capabilities.

Excellicon's Constraints Manager ConMan is based on patented formal technology targeted at solving complex problems facing chip designers, from initial planning through final timing closure where implementation expertise is needed. Its tools provide the infrastructure to develop, track, optimize and verify information for the entire design for faster time to tapeout. They also enable designers to seamlessly propagate constraints for any mode in the design to any layer of hierarchy with ease.

Since its founding in 1999, Verific's software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The Verific parser platform includes support for SystemVerilog, Verilog, VHDL and UPF. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

Verific is to demonstrate its RTL front-end solutions during DAC in booth #610 June 4- 6 at the Moscone Center in San Francisco.




Xilinx 7 series FPGA
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