Date: 26/04/2012

Advanced memory and logic tech and 3D TSV by SEMATECH at VLSI Sympo

SEMATECH experts have presented innovative approaches to realize advanced CMOS logic and memory semiconductor device technologies and 3D through-silicon via (TSV) manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA) on April 23-25, 2012.

SEMATECH's front end processes program is exploring innovative materials, new transistor structures, and alternative non-volatile memories to address key aspects of system-level performance, power and variability in the scaling of logic and memory applications.

Sitaram Arkalgud, director of SEMATECH's 3D Interconnect program revealed copper-to-copper direct bonding (CuDB) technology as a technology to scale chip-to-chip interconnects and keep pace with advances in TSV.

SEMATECH technologists reported technical advances in the following areas:

Silicon channel devices

1. Evaluating stress-induced leakage current (SILC) in full gate-last (FGL) high-k/metal gate devices to address sources of SILC and propose possible process options for improvement. A high-quality interlayer during gate stack formation was found to be critical to improving FGL device performance and reliability.
2. Modeling positive bias temperature instability (PBTI) degradation in Zr-doped HfO2 gate stacks by considering fast and slow electron trapping processes. PBTI was found to improve when the fast trapping component was suppressed.

Non-silicon channel devices

1. Using different ALD oxidizers to study the effects of III-V oxides on device performance. With a O3 precursor, As-As, AsOx, GaO, and In2O3 were found to be the main native oxides/byproducts. H2O-based precursors remain stable with no III-V oxide detected throughout a low temperature flow. Electrical performance also improved with H2O-based high-k, suggesting that H2O-based ALD is the key process for III-V CMOS.
2. Exploring alternative high-k gate dielectrics for III-V, Ge and Si MOSFETs. High-field carrier mobility and MOSFET parameter characteristics were improved by atomic layer deposition (ALD) of a thin beryllium oxide layer to passivate the interface between the Si channel and high-k gate dielectric.

Non-planar devices

1. Studying FinFET Vt tuning. Both performance and the electrical properties of the gate stack were improved by an Al implantation, representing progress towards realizing multi threshold voltage FinFET device architectures for the 14 nm node and beyond.
2. Studying the impact of fin doping on high-k/midgap metal gate SOI FinFETs. Threshold voltage can be effectively modulated with doping in ~25 nm wide fins. For sub-10 nm fin widths, however, the active dopant atoms must be precisely placed inside the fins, which ion implantation cannot do. A conformal doping technique with perfect dose control, such as monolayer doping, was discussed which may be the solution for future planar and non-planar devices.
3. Evaluating the parasitic capacitance of planar FETs and double-gated (DG) FinFETs. Optimization with a fixed fin-to-height ratio significantly reduces parasitic capacitance, which renders DG FinFETs comparable to planar FETs. Fin width and height must be controlled in the DG FinFETs, otherwise the parasitic capacitance uniformity will degrade.
4. Investigating the impact of source/drain (S/D) activation anneal on GAA pFETs. Low-temperature pFETs were fabricated and benchmarked against devices with a S/D activation anneal. When S/D is implanted before the gate spacer, the un-annealed devices exhibited higher peak transconductance and drain current but have a higher off-current than their annealed counterparts. Pre- and post-spacer S/D implant schemes were also explored.

Advanced non-volatile memory

1. RRAM switching performance up to 1x108 cycles at low power and a 100x reduction of the high-resistance-state current was achieved by identification and utilization of key parameters for establishing superior control of the RRAM conductive filament formation.

The consortium, called SEMATECH (SEmiconductor MAnufacturing TECHnology), was formed in 1987, when 14 U.S.-based semiconductor manufacturers and the U.S. government came together to solve common manufacturing problems by leveraging resources and sharing risks.