Date: 22/04/2012

Renesas Electronics adopts Synopsys' Proteus LRC for lithography verification

Renesas Electronics adopts Synopsys' Proteus LRC for lithographic verification to identify yield-impacting hotspots prior to committing a design to manufacture saving the chipmaker from the respinning effort.

"We require a highly accurate lithographic verification solution that has a low cost of ownership and and has ability to reduce our process development time," said Nobuyasu Yui, department manager, Analog Design Technology Development Department, EDA & Design Methodology Division, Technology Development Unit at Renesas Electronics Corporation. "The adoption of Proteus LRC for our leading-edge microcontroller has improved our optical proximity correction development efficiency contributing to faster time to market."

Proteus LRC uses ,optical proximity correction, resist profile and topography simulations for efficient layout processing and results analysis. Proteus LRC is a single-flow solution from design tapeout to mask fracture and efficiently handling of large terabyte datasets in advanced nodes.