Date: 11/04/2012

SMIC 40nm Reference Flow uses Cadence' Encounter

Cadence Design Systems has announced that China's Semiconductor Manufacturing International Corporation (SMIC) has introduced a low-power, advanced-node IC design reference flow using Cadence Encounter digital technology and SMIC's 40-nanometer manufacturing process.

"We have worked closely with Cadence to develop a reference flow that helps our customers accelerate and differentiate their low-power, high-performance chips," said Tianshen Tang, vice president of SMIC Design Service. "By using this interoperable, low-power, Common Power Format-based flow from RTL to GDSII, design teams can achieve faster time-to-volume for advanced low-power 40-nanometer designs."

"Cadence and SMIC have teamed to enable joint customers to benefit from a comprehensive set of digital technologies such as flat power aware implementation with timing and signal integrity closure, power domain aware physical synthesis, closed loop low-power verification and physical verification," said John Murphy, group director, Strategic Alliances at Cadence. "By using this proven flow with the 40-nanometer SMIC manufacturing process, customers have a differentiated approach to low-power design that can get them to market faster with lower power consumption."