Date: 11/04/2012

Multi-core processor on-chip communication goes serial and packet based

The power of processing by processor chips is now more about number of processor cores rather than the individual core capability. With a single computer system handling multiple tasks, the multicore is the choice to deliver faster computing through parallel computing.

With the quad-core is being norm now in desktop computer and a system with 100s of cores are in the pipeline, the challenge in multicore computing is on-chip connectivity between cores. The complex mutiwire parallel bus is now giving way to single wire packet routing technique used in Internet in connecting computers for efficient transfer of data.

Massachusetts Institute of Technology (MIT) researcher Li-Shiuan Peh (associate professor of electrical engineering and computer science at MIT) and her colleagues are trying out this new concept where the cores will communicate the same way computers wired to the Internet: by bundling the information they transmit into "packets." Each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network as a whole.

At the electronics design popular event Design Automation Conference (DAC) in June 2012, Peh and her colleagues to present a paper she describes as "summarizing 10 years of research" on such "networks on chip."

The release from MIT states "Not only do the researchers establish theoretical limits on the efficiency of packet-switched on-chip communication networks, but they also present measurements performed on a test chip in which they came very close to reaching several of those limits."

According to Peh "the buses have hit a limit, They typically scale to about eight cores." The 10-core chips found in high-end servers frequently add a second bus, but that approach won't work for chips with hundreds of cores, stated in the release.

Peh adds "buses take up a lot of power, because they are trying to drive long wires to eight or 10 cores at the same time." In the type of network Peh is proposing, on the other hand, each core communicates only with the four cores nearest it. "Here, you're driving short segments of wires, so that allows you to go lower in voltage," she explains.

The problem with on-chip network is, a packet of data traveling from one core to another has to stop at every router in between, if two packets arrive at a router at the same time, one of them has to be stored in memory while the router handles the other. Peh says

"Many engineers worry that these added requirements will introduce enough delays and computational complexity to offset the advantages of packet switching. The biggest problem according to her is that in industry right now, people don't know how to build these networks, because it has been buses for decades.

The solution by Peh's team is: One is something they call "virtual bypassing." In the Internet, when a packet arrives at a router, the router inspects its addressing information before deciding which path to send it down. With virtual bypassing, however, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. In her group's test chips, Peh says, virtual bypassing allowed a very close approach to the maximum data-transmission rates predicted by theoretical analysis.

Another technique is something called low-swing signaling. Digital data consists of ones and zeroes, which are transmitted over communications channels as high and low voltages. Sunghyun Park, a PhD student advised by both Peh and Anantha Chandrakasan, the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering, developed a circuit that reduces the swing between the high and low voltages from one volt to 300 millivolts. With its combination of virtual bypassing and low-swing signaling, the researchers' test chip consumed 38 percent less energy than previous packet-switched test chips. The researchers have more work to do, Peh says, before their test chip's power consumption gets as close to the theoretical limit as its data transmission rate does. "But if we compare it against a bus, we get orders-of-magnitude savings." She adds.

Luca Carloni, an associate professor of computer science at Columbia University who is working on this subject comments: The advantages of packet-switched networks on chip seem compelling. Advantages according to him includes not only the operational efficiency of the chips themselves, but also a level of regularity and productivity at design time that is very important.

With on-chip optical communication, the total processing power of processor is expected to increase further significantly in coming years.