Date: 01/04/2012

Synopsys along with IMTAB members develop models for double pattern analysis

Synopsys in collaboration with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has worked out a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing. The new DPT model extensions will be available to the EDA and semiconductor industries through the open source licensed Interconnect Technology Format (ITF) version 2012.06 ratified by IMTAB members, including Apache Design - a subsidiary of ANSYS, GLOBALFOUNDRIES, NVIDIA, Synopsys and others (the full member list is available at www.imtab.org).

Synopsys explains: DPT is a critical technique for ensuring printability of device and interconnect layers in 20-nm IC manufacturing. However, splitting layers into two masks can introduce timing variations as a consequence of mask misalignment in the manufacturing process. To enable successful 20-nm design tapeouts and manufacturing, the IMTAB members determined that a DPT-aware modeling solution for parasitic extraction was needed to account for the timing impact and address it in the physical implementation and signoff design flow.

"The real challenge was developing a solution that accurately modeled the impact on timing with no productivity change to the flow," said Bari Biswas, chair of IMTAB and senior director of engineering for extraction solutions at Synopsys. "While working with IMTAB and leading foundries, Synopsys developed a novel modeling technique that eliminates the need to insert the time-consuming coloring step during the implementation and signoff flow, with negligible impact on extraction runtime."

"The manufacturing requirements at advanced process nodes, such as double-patterning lithography at 20-nanometers, are driving an industry-wide, intensive focus on newer parasitic modeling techniques to achieve signoff accuracy and performance," said Richard Trihy, director of design methodology at GLOBALFOUNDRIES. "GLOBALFOUNDRIES is pleased to be working with the industry-leading IMTAB member companies and lending our extensive knowledge of advanced processes to develop innovative solutions that address these common challenges. Our close collaboration has resulted in several enhancements to ITF modeling at the 28-nanometer node, and GLOBALFOUNDRIES is now driving silicon-validation of the latest DPT modeling at the 20-nanometer node."

In addition to DPT modeling, IMTAB has also approved enhanced trench contact device modeling extensions in the ITF to include evolving 20-nm characteristics. The trench contacts are used for local device interconnections that improve density and lower resistance. However, additional challenges are introduced in modeling co-vertical conductors and associated large fringe capacitances. To deal with these issues, specific 20-nm extensions were added to explicitly model silicon dielectric underneath the device and the special dielectric region between the gate and raised diffusion to enable accurate modeling of the new parasitic effects.

"IMTAB members continue to collaborate on challenges facing the semiconductor industry in new process nodes such as 20-nanometer," said Marco Migliaro, president and CEO at IEEE-ISTO. "To improve tool interoperability around ITF modeling, IMTAB will help the industry realize a single, proven format to help speed design flows."

Synopsys also said it is collaborating with Altera and TSMC to silicon-validate modeling of key parasitic effects in Synopsys' StarRC solution for TSMC's 28-nanometer (nm) processes. The StarRC solution achieved the stringent model-to-silicon accuracy criteria of TSMC's 28-nm process technology to enable high-performance designs at the advanced node. Altera Corporation, a pioneer in programmable logic, has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28-nm FPGA designs.

Synopsys has claimed StarRC parasitic extraction solution has enabled more than 150 successful 28-nanometer (nm) tapeouts and StarRC is used by more than 40 semiconductor companies for 28-nm design signoff. Companies that have qualified and selected the StarRC solution for use in their 28-nm signoff and tapeout flows include Altera Corporation, Bull, Fujitsu Semiconductor, HiSilicon Technologies, Imagination Technologies, LSI Corporation, Moortec Semiconductor, NVIDIA, Qualcomm Incorporated, Renesas Electronics Corporation, Samsung, STMicroelectronics, Toshiba and others, as per Synopsys.

"We have collaborated closely with Synopsys through several generations of process nodes to accurately model complex parasitic effects and qualify StarRC for TSMC's advanced process technologies including 28-nanometer," said Suk Lee, senior director of design infrastructure marketing at TSMC. "We are pleased to see our mutual customers, such as Altera, realize the benefits of this collaboration and deploy the solution to achieve a high standard of accuracy on their leading-edge 28-nanometer designs."

Another leading EDA vendor Cadence Design Systems, Inc. has recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for designing semiconductor chips at 20nm nodes supporting double patterning tech.