Date: 13/02/2012

Maskless lithography: a better alternative in semiconductor chip fab tech

Due to the ultra-complexity of the present multi-mask lithography based IC fab tech, its natural for a semiconductor fabrication expert to think about modulating the light beam in 3axis rather than using multiple number of photo masks to print patterns on photoresistive material to etch the semiconductor material with gate, drain and source terminals of MOSFET. If the beam is moved on the silicon at nano meter scale very fast, so that the number of wafers handled is as good as mask type lithography, it makes sense for mass adoption of maskfree lithography. In fact the light beam is no more viable and is replaced with electron-beam in maskless lithography, electron beam's x,y,z coordinates can be better controlled electrically than a light beam. It's like controlling the electron beam in cathode ray tube where the beam hits the big phosphor screen. The similar technique is applied to chip making, where the electron beam is moved over small area of silicon in nano meter (nm) scale.

The challenge here is precisely controlling the electron-beam at a speed what the present chip industry demands. Also shooting enough number of electrons in short time for effective etching of the surface.

The France based research institute CEA Leti along with its partner Mapper has disclosed some breakthrough achievement in maskless lithography in making semiconductor chips. But they use parallel technology with massively parallel multiple beams.

The major achievement reported by CEA Leti is in achieving resolution: 22nm dense lines and spaces and 22 nm dense contact holes (see pic down below) in positive chemically amplified resist have been successfully resolved. The release stated this demonstrated resolution also meets the industry requirement for the next generation 14 nm and 10 nm Logic technology nodes.

CEA-Leti is one of the MAPPER's first pre-production Matrix systems user, offering global players to assess maskless lithography technology in a real manufacturing environment.

The multi-partner program IMAGINE is an initially three-year project led by CEA-Leti, and includes leading semiconductor fab service provider TSMC and leading chipmaker STMicroelectronics.

Laurent Pain, coordinator of the IMAGINE program and manager of the CEA-Leti lithography laboratory said "This technology represents a real alternative for advanced semiconductor manufacturing"
.
Bert Jan Kampherbeek, CEO, MAPPER says "In 2012 MAPPER will complete its Matrix pre-production platform with initially a 1 wafer per hour throughput capability and scalable to 10 wafers per hour."

The IMAGINE project is an initially three-year project led by CEA-Leti, evaluating a maskless lithography infrastructure and the use of MAPPER Lithography tools for high throughput. The multiple e-beam-lithography program covers a global approach to the technology, including tool assessment, patterning and process integration, data handling, prototyping and cost analysis.

Participants in the IMAGINE also includes companies such as Nissan Chemical, TOK, Dow, JSR Micro, Synopsys, Mentor Graphics, Sokudo, Tel and Aselta.
mask less litho