Date: 16/11/2010

Toshiba develops tech for embedded SRAM to operate from wide Vcc of 0.5V to 1.0V

Toshiba Corporation has announced it has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to 1.0V, that effectively contribute to lower power consumption by electronic devices. The test semiconductor chip fabricated employs three new techniques to ensure proper operation of SRAM even when the operating voltage varies.

They are explained below by Toshiba:

Embedded SRAM in LSI for mobile equipment has multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes. Toshiba's new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.

When sense amplifier activation timing is adjusted to the slowest cell in low-voltage operation, it becomes too slow in high-voltage operation and SRAM performance slows. The new technique controls wordline voltage so that the voltage characteristics of the control circuit, which determines the sense amplifier activation timing, match the slowest cell's voltage characteristics. Consequently, activation at the optimum timing is possible at any operating voltage. This technique improves the activation timing in high-voltage operation even if the sense amplifier activation timing is optimized at the lowest operating voltage, resulting in an 18% improvement in operating frequency.

Another issue is an increased malfunction rate for SRAM cells affected by bit lines in read/write operations at low voltage, such as below 0.7V. Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, achieving operation at voltage as low as 0.5V, although available memory capacity is reduced.

Need of this chip design technology as explained by Toshiba: As the process node advances, however, it is becoming difficult to achieve stable operation of SRAM used for cache memory in LSI at low operating voltage. Therefore, techniques that can ensure stable operation even at low voltage and optimize performance in accordance with voltage variation are required. The techniques Toshiba has developed achieve both low power consumption and stable operation by adding a small number of circuits.