Date: 14/11/2010

Mentor Graphics' Questa and Veloce to support latest ARM Cortex and AMBA

Mentor Graphics Corporation has announced that its Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces.

The Mentor library of accelerated Instruction Set Simulation (ISS) models that currently includes all ARM Cortex A-family, Cortex R-family, and Cortex M-family processors, has added support for ARM's newest Cortex A7 MPCore and Cortex A15 MPCore products. Multi-core SoC designs incorporating these processors can now be verified across both the Questa and Veloce verification platforms with the Questa Codelink product's unique 'DVR-style' of simulation/emulation playback for debugging. Engineers can combine their RTL processor models with the ISS processor models, which can be hot-swapped, on-the-fly during simulation.

Mentor has also expanded its library of verification IP (VIP) with the addition of AMBA 4 ACE support to Questa Verification IP.

"We have worked directly with ARM and mutual customers to put in place verification solutions that enable designers to design and verify next generation SoCs that leverage ARM's big.LITTLE processing," said John Lenyo, general manager of the Design Verification Technology division of Mentor Graphics. "Our unique Questa and Veloce functional verification platforms, optimized to support multi-core hardware and software verification, enable a new class of SoC-Level Verification that allows our users to deliver on their first-to-market plans."