Date: 13/10/2011

Synopsys' DesignWare IP for UMC's 28nm HLP Poly SiON process

United Microelectronics Corporation and Synopsys have expanded their collaboration to develop DesignWare IP for UMC's 28-nanometer (nm) HLP Poly SiON process.

"UMC and Synopsys' close collaboration has spanned many years and technology generations," said S. C. Chien, UMC vice president of Customer Engineering & IP Development Design Support Divisions. "Extending our relationship with Synopsys, a leading and trusted IP provider, into the 28-nm process shows our mutual commitment to helping customers develop their increasingly complex SoC designs. We look forward to bringing these next-generation products to market with our customers."

"Synopsys' collaboration with UMC, a leading foundry provider, will help our mutual customers differentiate their SoC designs with IP that is proven in UMC's robust 28-nm process technology," said John Koeter, vice president of marketing for IP & systems at Synopsys. "Our extensive track record of delivering high-quality IP in advanced nodes gives designers confidence that they can integrate DesignWare IP into their SoCs with less risk and achieve a predictable path to first-pass silicon success."

Availability: The DesignWare Embedded Memories and Logic Libraries supporting UMC's 28HLP process are scheduled to be available in Q2 2012. The 28HLP DesignWare Embedded Memories and Logic Libraries will be available at no cost to qualified licensees as part of Synopsys' Foundry Sponsored IP program. UMC's 28-nm Poly SiON technology is available for customer pilot production now.