Date: 26/08/2011

JEDEC advances DDR4 Standard with reduced power usage

JEDEC Solid State Technology Association has selected key attributes of its widely anticipated DDR4 (Double Data Rate 4) standard. With publication forecasted for mid-2012, JEDEC says DDR4 will represent a significant advancement in performance with reduced power usage as compared to previous generation technologies.

DDR4 is being developed with features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products and its speed, voltage and architecture are defined with the simplifying migration and facilitating adoption of the standard, says JEDEC.

A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.

The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups, which will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups and this concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used, as per JEDEC.

Additional features in development include:
Three data width offerings: x4, x8 and x16
New JEDEC POD12 interface standard for DDR4 (1.2V)
Differential signaling for the clock and strobes
New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
Burst length of 8 and burst chop of 4
Data masking
DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
New CRC for data bus: Enabling error detection capability for data transfers - especially beneficial during write operations and in non-ECC memory applications.
New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
DLL off mode supported

Joe Macri, Chairman of JEDEC's JC-42.3 Subcommittee for DRAM Memories, said "Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption." He added, "JEDEC invites all interested companies worldwide to participate in the development of DDR4. The next committee meeting will be held in Chicago in September 2011.
For more information visit www.jedec.org