Date: 17/07/2011

Online low-power VLSI chip design webinars from Apache

VLSI EDA software vendor Apache Design Solutions has announced the schedule for their upcoming online low-power webinar series.

The low-power webinar series presented by Apache's Power Team Experts will cover the company's comprehensive power methodologies that deliver power budgeting, IP integration and chip-package-system solutions to address the complex power challenges faced by integrated circuit (IC) designers today.

The low-power webinar series schedule dates and topics are listed below.

Ultra-Low-Power Methodology
Tuesday July 19, 2011, 11:00AM - 12:00PM PDT

IP Integration Methodology
Thursday, July 21, 2011, 11:00AM - 12:00PM PDT

PowerArtist - RTL Power Analysis, Reduction, and Debug
Tuesday, July 26, 2011, 11:00AM - 12:00PM PDT

RedHawk - SoC Power Integrity and Sign-off for 28-nm Designs
Thursday, July 28, 2011, 11:00AM - 12:00PM PDT

Totem - Analog/Mixed-Signal Power Noise and Reliability
Tuesday, August 2, 2011, 11:00AM - 12:00PM PDT

PathFinder - Full-chip ESD Integrity and Macro-level Dynamic ESD
Thursday, August 4, 2011, 11:00AM - 12:00PM PDT

Chip-Package-System (CPS) Convergence Solution
Tuesday, August 9, 2011, 11:00AM - 12:00PM PDT

Sentinel-PSI - IC-Package Power and Signal Integrity Solution
Thursday, August 11, 2011, 11:00AM - 12:00PM PDT

To know more visit www.apache-da.com