Date: 17/07/2011

OpenFlow 1.1 Implemented on Ezchip's NP-4 100Gb network processor

EZchip Semiconductor Ltd. has announced the implementation of OpenFlow spec, version 1.1 on its NP-4 network processor device by several independent bodies. OpenFlow separates the data and control planes in a switched network for increase network functionality.

One of the implementations of OpenFlow 1.1 on the NP-4 was developed by the Telecom Research Team (LTIR Lab) at the Université du Québec à Montréal (UQAM). EZchip did not disclose names of other companies who have implemented due to confidentiality. The LTIR Research Lab was founded by Professor Omar Cherkaoui who is leading a major project on the virtualization of network equipment called Netvirt.

"EZchip's NP-4 processor provides the flexibility and performance necessary for implementing OF1.1 as well as any future versions of the standard. NP-4's easy programming model enabled the UQAM Netvirt team to realize our OF1.1 full implementation with a high level of flexibility and a full 100 Gigabits. We are very pleased with the outcome," said Prof. Omar Cherkaoui, Université du Québec à Montréal.

A demo summary of the related work using EZchip's NP-4 performed by UQAM can be downloaded at http://groups.geni.net/geni/attachment/wiki/GEC10DemoSummary/UQAM-Openflow-Genidemo-Poster_V_1.0.pdf

While the previous version of OpenFlow, version 1.0, has seen multiple silicon-based implementations, the recently released version 1.1 strains silicon implementations by requiring a high degree of packet processing flexibility, in particular performing repetitive nested lookups in various tables. Ezchip says its network processors (NPUs) have long been recognized as providing a great degree of packet processing flexibility through software programming and without requiring any special hardware enhancements or revisions.