Date: 12/07/2011

Synopsys IC compiler supports DPT tech for 20nm IC design

Synopsys, Inc. has announced new IC Compiler physical design product called IC Compiler-Advanced Geometry targeting design support for double-patterning technology (DPT), which has emerged as a key requirement for the next generation of silicon technology at 20 nanometers (nm) and imposes strict constraints on placement, routing and physical verification.

The current lithography approach supporting IC manufacturing reaches a theoretical limit at the 20nm node, making it difficult to achieve minimum resolution for silicon structures. There are two possible approaches: 20nm design must either adopt a resolution that is sparser than minimum, and therefore not silicon-efficient; or the design must be split into two sets of alternating structures, each more sparse than minimum but together fully utilizing available silicon resource. The latter, termed double-pattern technology, requires a place-and-route tool to accurately generate a layout where each candidate layer can be decomposed into dual alternating patterns without undue impact on performance and device area.

Synopsys says the new configuration of IC Compiler includes innovative technology to formulate double patterning requirements as a generalized coloring problem, avoiding any potential conflicts and rendering a correct-by-construction solution that can be reliably decomposed during manufacturing. Synopsys has enhanced its IC Compiler's placement engine and its Zroute technology, which have both been enhanced to be DPT-driven. In addition, IC Validator's In-Design Physical Verification has been enhanced for DPT compliance, enabling IC designers to verify before handoff to manufacturing that target layers in the design are decomposable.

"Design and manufacturing complexity continues to rise, and designers are under increased pressure to adapt and deliver. As a result, it is imperative that we collaborate closely with our foundry partners and key customers to be the first to offer a compelling design implementation solution," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "IC Compiler-Advanced Geometry is the industry's first DPT-compliant place-and-route solution that will provide designers moving to 20 nanometers with an advanced solution that effectively meets the new challenges."

Synopsys, Inc. has also announced that it has collaborated with Samsung Electronics for taping out the first 20-nanometer (nm) test chip based on Samsung's High-k metal gate (HKMG) process technology. The test chip was implemented using Synopsys' Galaxy Implementation Platform, including the Design Compiler synthesis, IC Compiler place-and-route, In-Design physical verification with IC Validator, StarRC extraction and PrimeTime signoff tools.

Dr. Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics said "We are collaborating closely with Synopsys to enable the timely availability of innovative components in our 20-nanometer design infrastructure. Synopsys' technology leadership enabled us to quickly implement and validate our first 20-nanometer test chip. The successful tapeout of this test chip marks a critical milestone towards design readiness for our 20-nanometer process technology."