Date: 12/07/2011

Imec brings down the leakage current in DRAM at lower EOT of 0.4nm

Imec said it has made breakthroughs in making of both DRAM and RRAM memory devices. Imec has demonstrated a novel RuOx/STO/TiN stack that showed a 100x reduction in leakage with DRAM MIMcap (metal-insulator-metal capacitor) compatible dielectrics at 0.4nm equivalent oxide thickness (EOT). Imec said it has achieved a further 10x improvement by optimizing the stack, resulting in a record leakage current density (JG) of 2x10-8A/cm² at 0.4nm EOT. This allowed a path to demonstrate a further potential through lowering the trap density, to a theoretical leakage current density (JG) limit for trap-free STO of 10-15A/cm² at ~0.4nm EOT. Imec claims STO-based stack is a promising technology for DRAM scaling.

In RRAM, a dielectric, which is normally insulating, can be made conductive through a filament or conduction path formed by applying a sufficiently high voltage. Imec said it has now made breakthroughs in understanding the properties of the filaments. Imec established a.o. that the minimal achievable current after reset depends on the physical nature of the filaments, resulting in a direct method to predict that current from the filament properties. With these results, it is now possible to choose the desired properties of the filaments to ensure a stable RRAM operation.