Date: 24/06/2011

Cadence demos PCI Express 3.0 at PCI-SIG Developers Conference

Cadence Design Systems, has announced it has showcased PCI Express 3.0 solutions at the 2011 PCI-SIG Developers Conference held at Santa Clara Convention Center, Santa Clara, CA

Cadence' demo includes design and verification IP that supports v1.0 of the PCI Express 3.0 specification. Cadence has highlighted its PCI Express 3.0 controller IP, as well as verification IP and design-in kits for package-to-board implementation.

Design IP Demonstration:
Cadence demonstrated high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration implemented in silicon on an advanced-node PMC-Sierra ASIC. The Cadence PCI Express 3.0 controller is integrated in an ASIC on a reference card, which connects to a PCI Express Gen3 backplane exerciser and a PCI Express Gen3 logic analyzer to demonstrate PCI Express 3.0 traffic running at 8 GT/s per lane. Complying with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification, the Cadence PCI Express 3.0 design IP has been successfully implemented in silicon with advanced capabilities like Single-Root I/O Virtualization (SR-IOV) and the latest engineering change notices (ECNs) such as ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.

Verification IP Demonstration:
Cadence has also demonstrated its PCI Express 3.0 VIP solution. The demonstration is how the unique Compliance Management System (CMS) for the PCI Express protocol which provides interactive, graphical analysis of coverage results correlated directly to the protocol specification, and PureSuite which provides thousands of test cases to simulate PCI Express traffic and check for compliance with the PCI Express specifications.