Date: 09/06/2011

imec-Cadence collaboration offers DFT and ATPG test solutions for 3D semiconductor Ics

Imec and Cadence Design collaboration is offering the design-for-test (DFT) and automatic test pattern generation (ATPG) technology to test 3D semiconductor ICs with "through-silicon via" (TSV) functionality and help ensure that the stacked system will work as intended.

The stacking of semiconductor ICs is the new challenge and market opportunity for semiconductor-chip makers. Quality and reliable test tools save significant time for 3D IC developers.

The 3D DFT architecture is based on the concept of die-level test wrappers, which enable testing of chips with TSVs and micro-bumps both before ("pre-bond test"), during ("mid-bond test"), and after ("post-bond test") stacking, as well as after packaging.

"This new DFT solution is the latest example of our commitment at Cadence® to the emerging area of 3D-IC," said Brion Keller, senior architect at Cadence. "Over the past two years, we've introduced 3D-IC TSV and silicon interposer capabilities, and, just three months ago, the industry's first wide I/O memory controller IP solution, with a robust 3D-IC integration environment. Collaboration is an essential element of effective Silicon Realization and the EDA360 vision we adhere to, and this initiative with imec demonstrates why."

"Using 3D-IC and TSV technology, electronics companies look forward to creating a new generation of super chips," said Erik Jan Marinissen, principal scientist at imec. "The imec-Cadence offering inserts DFT structures with minimal area overhead, and the ATPG method helps drive towards zero manufacturing defects on the TSVs. This unique offering reduces risk and promotes cost-effective fabrication of these chips."

Cadence and imec created the design flow automation for adding 3D-enhanced IEEE 1500-based die wrappers to existing chip designs. This was done by enhancing the existing IEEE 1500 wrapper insertion support in the Cadence Encounter RTL Compiler synthesis product. Initial results on customer designs showed that the 3D DFT structures can be implemented with negligible area costs-about 0.2%, which is far less than what some in the electronics industry have been speculating, says Cadence.