Date: 30/05/2011

Sibridge's verification IPs are integrated with Axiom's MPSim 5.0

Sibridge Technologies and Axiom Design Automation have announced a partnership agreement to help their customers to speed up SoC class semiconductor chip design & verification.

Sibridge's Verification IP (VIP) for industry-standard interfaces including PCI Express Gen 1.1, 2.0, 3.0, Ethernet 10G/1G/100M/10M, USB 2.0/3.0, AMBA AHB/AXI and I2C are integrated with Axiom's MPSim 5.0. Axiom's MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture.

"The partnership will enable our mutual customer with comprehensive verification solutions to accelerate silicon success by reducing the verification time", said Rajesh Shah, CEO, Sibridge Technologies. "Customer can now rely on the very best VIP and industry proven EDA tools to streamline their chip design and verification process with an added advantage of comprehensive support and integration services" added Rajesh Shah.

"The partnership perfectly fits our strategy to offer the most comprehensive and integrated verification platform to our customers", stated Badru Agarwala, President and CEO of Axiom Design Automation. "Due to its superior performance, productivity and predictability capabilities, MPSim is fast becoming the verification platform of choice for verification of complex SoCs and many of our customers have very large verification farms based on MPSim for regression testing. Now integrated with a large portfolio of complex verification IPs, Axiom's flexible business model offers our customers unsurpassed flexibility in developing and deploying the best price performance verification and regression environment for complex designs".