Date: 25/05/2011

Imec and Atrenta develop exploration flows for 3D Ics

Atrenta Inc & imec's 3D integration IIAP (industrial affiliation program), are jointly developing an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs, to address the growing trend of vertical integration.

The flow under development is designed for minimizing the number of design iterations, facilitating a cost- and time-effective search of the solution space. Imec and Atrenta demonstrated their first EDA tool flow dedicated to 3D design exploration at last year's DAC.

3D stacked ICs offers advantages of reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. Some of the immediate applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

The design aspects of 3D stacked semiconductor chips involve:
1. Early planning and partitioning.
2.Selectivity of right solution such as front to front, front to back, silicon interposer, technology choice for slices, via configurations, and partitioning.
3.Performing robust, accurate partitioning and prototyping early in the design process, well before detailed implementation begins.
4.Thermal profiles (heat dissipation) and the mechanical stress caused by assembly configurations.

Imec said it has developed compact thermal and mechanical models for rapid generation of heat dissipation and mechanical stress maps and has validated them using real 3D DRAM-on-logic packaged devices. When combining the design floor plans produced by Atrenta's SpyGlass Physical 3D prototyping tool with the stress models developed by imec, different scenarios can be assessed quickly and the best option can be chosen in advance of a full design implementation as per these companies.

Imec and Atrenta will be demonstrating the newest version of their advanced 3D planning and partitioning design flow in the Atrenta booth (1643) at DAC. The demonstration will include design partitioning across a 3D stack with routing congestion analysis, through silicon via (TSV) placement and backside redistribution layer routing support as well as display of thermal profiles on the 3D floor plan.
For more information about Atrenta's demonstrations at DAC visit:
http://www.atrenta.com/DAC2011/sessions_short.html