Date: 09/03/2011

Technical workshop on power and noise issues in chip-package-system

Apache Design Solutions has announced that it will host two educational Technical Workshops during the upcoming DATE 2011 conference being held at AlpExpo in Grenoble, France. The Apache Technical Workshops will take place during the conference on March 15, from 14:00 p.m. to 15:00 p.m., and on March 16, from 12:30 p.m. to 13:30 p.m., in meeting room 7 Laux 4.

This informative Technical Workshop series will cover two specific topics. The first session on March 15 will focus on "Chip-Package-System Methodology from Early Stage to Sign-off," featuring the impact of power and noise on overall system cost and performance, and how a proven CPS methodology addresses the power integrity and power induced noise challenges facing today's engineers. It will detail the modeling, extraction and analysis technologies, as well as efficient model exchange capabilities, required for bringing together SoC, IC package, and system designers to meet their system cost and performance targets.

The second session on March 16 will feature "Power Methodology for Energy Efficient Designs," highlighting Apache's broad portfolio of power and noise analysis platforms addressing the needs of low power, energy efficient designs. It will discuss RTL power analysis, reduction and debug, custom IP validation and model creation, and SoC integration, optimization and sign-off, to ensure power budgets are met while maintaining design integrity. This workshop also features advanced reliability challenges, such as ESD and power, signal and thermal integrity needs of 3D IC designs.

Admission to the workshop is complimentary for DATE conference and exhibit attendees, but advance registration is required and seating is limited.

To know more visit www.apache-da.com