Date: 09/03/2011

Yokogawa enhance its PLC Performance by using Synopsys' processor designer

Synopsys saysYokogawa Electric Corporation has used Synopsys Processor Designer to achieve ultrafast ladder program processing performance for their latest FA-M3V programmable logic controller (PLC). As per Synopsys, Yokogawa also saved significant development and verification effort with Processor Designer since the tool automatically generates software development tools such as C-compiler, assembler/linker, debugger and the instruction set simulator (ISS) needed for early software development prior to processor availability.

"Our new PLC FA-M3V has achieved the fastest performance we've ever seen with our latest 'Vitesse Engine' core customized for ladder language program processing," said Hirofumi Okamoto, group leader of the PLC Development Division, Yokogawa Electric Corporation. "With Processor Designer, we were able to develop this ultra-high performance processor using significantly less time and effort than we originally planned."

Processor Designer speeds up the development of design of both application-specific processors and configurable accelerators, which are used in development of system-on-chip (SoC) devices. Processor Designer supports design of architectures with DSP and RISC-specific features as well as single instruction multiple data (SIMD) and very long instruction word (VLIW) processors.

"Customers like Yokogawa are finding they can save significant development effort and achieve better quality of results by automating the application-specific instruction-set processor (ASIP) design process," said John Koeter, vice president of marketing for IP and systems at Synopsys. "With Processor Designer, companies developing ASIP or fixed processing hardware in-house gain broad architectural flexibility to deal with evolving requirements without compromising performance, power or area."