Date: 27/02/2011

TI and MIT researchers solve VLSI design issues of a DSP processor operating at 0.6V

Texas Instruments (TI) and the Massachusetts Institute of Technology (MIT) recently presented a joint research paper detailing design methodologies for a 28-nanometer (nm) mobile applications processor at the 2011 International Solid-State Circuits Conference (ISSCC). The papers presented at ISSCC are some of the best semiconductor technologies which going to influence the semiconductor products going to be released in next two years. The paper-"A 28nm 0.6V Low Power Digital Signal Processor (DSP) for Mobile Applications"-demonstrates that a DSP is capable of scaling from high-performance mode at 1.0 volts down to an ultra-low power (ULP) mode at 0.6 volts (V).

"As the multimedia and computing capabilities of TI's OMAP platform-based smartphones, tablets and other mobile devices increase, there is a continually expanding gap between performance demands and battery capacity," said Gordon Gammie, Distinguished Member of the Technical Staff at TI and ISSCC presenter. "TI believes that 28nm process technology advancements, developed in tandem with TI and MIT's low power circuit and methodology collaboration, gives us the right knowledge base to successfully meet the next-generation processing demands within the future mobile power envelope."

TI and MIT have developed new methodologies to address the challenge of low-voltage functionality and timing closure in the face of process variations without sacrificing high-voltage performance at nominal voltage. Researchers have developed standard cell library and custom low-voltage memory using novel ULV design methodologies are developed to be robust at 0.6V.

The delay distribution of standard cells at low voltages is no longer a Gaussian random variable. Traditional Statistical Static Timing Analysis (SSTA) tools based on a Gaussian distribution can suffer from 10-70 percent underestimation of delay at 0.6V. A newly developed SSTA technique has been shown to improve the accuracy of design timing at ULV to less than eight percent. The ability to accurately analyze low-voltage timing avoids excessive design margins and minimizes impact to area and high-voltage performance.

"The design of a low-voltage processor in 28nm requires a system-level approach - from optimizing the circuit styles and memories to the development of a custom low-voltage timing flow," said Anantha Chandrakasan, MIT professor and pioneer in the area of low-power design. "This chip demonstrates an aggressive low-power methodology to ensure robust low-voltage and ultra-low-power operation for a smartphone application processor."

"This is an excellent example of the results that come from a long and fruitful collaboration between a university and corporation such as MIT and Texas Instruments," said Gene Frantz, Principal Fellow at TI. "The students benefit by demonstrating their innovations on complex, DSPs with several million transistors made in state-of-the-art CMOS. TI and its customers benefit from early access to the students' innovations."
learn more about TI's advanced CMOS development by visiting www.ti.com/issccpr-cmos.

Also at this year's ISSCC, imec, Holst Centre and NXP Semiconductor have presented very low power consuming ECG signal processor named CoolBio, which consumes only 13pJ/cycle when running a complex ECG (electrocardiogram) algorithm at 1MHz and 0.4V operating voltage. This C-programmable chip is voltage and performance scalable supporting a frequency range of 1MHz up to 100MHz with an operating voltage from 0.4 to 1.2V. To know more on this read separate article titled "Complex processor for wearable medical electronics operate from 0.4 V"

The clear trend in SoC class semiconductor chips for applications such as medical electronics is to make the chips operate at low voltages of less than or equal to 0.6 V and allow them to consume only micro Amps or even pico amps of current.