Date: 20/02/2011

Free design seminar for semiconductor design experts in India from Atrenta

Atrenta, an expert in the VLSI design tool for validating RTL and optimizing IC designs has announced that it will host seminars in Bangalore, India and Hsinchu City, Taiwan to share the latest technologies and methodologies for Early Design Closure. Semiconductor chip designers in Bangalore India can leverage this event to learn various aspects of advanced chip design.

In the free full-day seminars, experts from Atrenta and noted industry veterans will present useful, in-depth information on power management, modeling of physical effects at RTL, clock domain crossing verification, design for test, constraints analysis and SoC assembly methodologies for IP and architecture reuse. Atrenta says this seminar will provide valuable information for engineering managers, chip architects, RTL designers, design methodology specialists and IP design/verification engineers seeking to rapidly implement correct designs through the integrated use of a variety of design automation solutions.

"We're delighted to take our popular design technology seminars to Banglaore and Hsinchu City and share Atrenta's expertise in Early Design Closure," said Mike Gianfagna, vice president of marketing at Atrenta. "These seminars are led by Atrenta's technology experts and noted veterans from industry and academia. We expect that participants will gain useful knowledge on innovative design technology that optimizes advanced SoCs before expensive and time-consuming detailed implementation begins. The result is accelerated time-to-market and reduced cost."

Pre-registration is required for these events. To register for one of Atrenta's no-cost sessions, please visit the links below.
http://www.atrenta.com/NewsLetter/newsletters/seminarblr-mar-2011.html

Seminar Schedule: Achieving Early Power & Physical Closure, Thursday, March 10, 2011 in Bangalore, India