Date: 01/02/2011

Xilinx joins GigaChip alliance

Xilinx has joined the GigaChip Alliance, an ecosystem of companies that support the GigaChip Interface whose participants include MoSys, Altera, NetLogic Microsystems.

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance not achievable using currently available serial protocols. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late '90s, MoSys believes the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology. According to MoSys a 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times.

"As the world's leading provider of programmable solutions, we are pleased to join the GigaChip Alliance and plan to support the GigaChip Interface in our FPGAs," said Sanjay Charagulla, Director, Corporate Strategic Planning at Xilinx. "We see a major trend towards serial chip-to-chip communications and believe the GigaChip Interface provides the efficiency and openness that our customers require."

"We couldn't be more pleased to have Xilinx join the GigaChip Alliance to support the proliferation of the GigaChip Interface into next generation networking systems," stated David DeMaria, Vice President of Business Operations for MoSys. "Our goal is to revolutionize serial chip-to-chip communications with the GigaChip Interface. Towards that end, we are making the GigaChip Interface an open protocol and encouraging widespread use by potential partners and customers. The GigaChip Alliance will facilitate industry-wide adoption and evolution of this protocol."

At the DesignCon 2011 MoSys and Xilinx will be demonstrating interoperability between the MoSys Bandwidth Engine(R) IC and Xilinx FPGAs using the GigaChip Interface.