Date: 01/02/2011

Rambus achieves differential memory signaling of 20Gpbs

Rambus has achieved differential signaling for SoC-to-memory interfaces to a new 20 gigabits per second (Gbps) and also able to achieve single-ended memory signaling of 12.8Gbps. Rambus calls this breakthrough. Rambus has also developed innovations which enable a seamless transition for memory architectures from single-ended to differential signaling.

Rambus says the latest technology advancements of its Terabyte Bandwidth Initiative enable unmatched power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins, adds Rambus. Rambus claims it has achieved a power efficiency of 6 milliwatts (mW) per Gbps when operating at 20Gbps in a 40nm-process silicon test vehicle.

"We have paved multiple paths for the industry by providing solutions that extend single-ended signaling beyond today's limits and developing the means for a seamless transition to differential signaling," said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus. "By advancing data rates in an extremely power-efficient way, and enabling compatibility to current industry-standard memories, we have removed the technical and business barriers for customers to achieve unprecedented capabilities in their products."