Date: 12/11/2010

Cavium does timing analysis of its OCTEON II processor using Synopsys's NanoTime software

At the nano meter geometries and the frequencies of 1.5 GHz, tracing the clock and other timing signal inside a complex SoC is more difficult than finding needle in a haystack. If proper tools are not used the VLSI designer will get lost in resolving timing bugs.

One among the popular EDA tools for timing analysis is Synopsys’ NanoTime transistor-level static timing analysis (STA) EDA software tool for testing timing part of complex semiconductor chips. This tool got the user approval for its performance. The user is multicore processor chip developer Cavium.

“As a leader in power-efficient internet networking solutions, we require a comprehensive static timing solution that addresses both gate- and transistor-level blocks, and a quality of results that gives us a high-level of confidence that the designs have been exhaustively verified within the development timeframe,” said Anil Jain, Corporate VP, IC Engineering at Cavium Networks. “NanoTime’s integration with the Synopsys PrimeTime suite provided us with extra precision and coverage in timing analysis and a comprehensive solution to achieve full-chip STA signoff.”