Date: 19/10/2010

NVIDIA adopts Mentor's Olympus-SoC product for its graphics processors

Mentor Graphics Corporation has announced that NVIDIA has adopted the Mentor's Olympus-SoC product for multi-corner, multi-mode (MCMM) design closure of their high performance graphics processors.

"We build some of the world's largest and highest performance ICs and it's crucial for us to maintain design schedules in the face of increasing IC complexity," said Sameer Halepete, vice president of ASIC Engineering at NVIDIA. "We have used Olympus-SoC on multiple GPU tapeouts and are very impressed with the overall quality of results and design schedule savings."

"We are very pleased with NVIDIA's success and its decision to standardize on Olympus-SoC for physical implementation and optimization," said Pravin Madhani, general manager for the Place and Route group at Mentor Graphics. "Olympus-SoC's unique architecture, high capacity data model and efficient multi-corner, multi-mode design closure capabilities continue to drive its adoption across various IC growth segments such as mobile, wireless, networking and graphics."

Mentor's web page on this VLSI design tool says, Olympus-SoC ensures optimization of the overall solution without excessive iterations. Some of the other features listed include automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing.

To know more visit http://www.mentor.com/products/ic_nanometer_design/place-route/olympus-soc/