Date: 17/09/2010

SynaptiCAD updates its Verilog netlist editor GOF to support logic equivalence failure correction

VLSI EDA tool vendor SynaptiCAD has updated its Verilog netlist editor, Gates-on-the-Fly (GOF). The GOF now supports easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence's Conformal LEC or Synopsys's Formality. SynaptiCAD has also published a white paper, Gates-on-the-Fly fixes Logic Equivalence Check Failures, that describes how the updated GOF was used to find and fix failures indentified by Cadence's Conformal tool at a customer site.

Verilog HDL is the most widely used HDL with a huge user community, it allows designers to design at various levels of abstraction.

GOF graphically analyzes and edits Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. The GOF uses the "incremental schematic" technology to find, view, and edit specific logic cones in the design on a schematic to visualize just the paths you need to see without unnecessary clutter. GOF is available on both Windows and Linux platforms.

Price: A perpetual license sells for US$5000 on Windows. Leasing options are also available.