Date: 08/07/2010

Fine pitch copper pillar flip chip packaging tech jointly by TI and Amkor

Amkor and Texas Instruments have attained qualification and has begun production of fine pitch copper pillar flip chip packages thus shrinking bump pitch up to 300 percent compared to current solder bump flip chip technology. These packages provide fine pitch input/output (I/O) pad structures of less than 50 microns. These packages are suggested for wireless and embedded processing applications based on plated copper pillar bumping and assembly technology.

"As chip I/O density increases with each process node, we had to find a way to decrease the distance between pins," said Tom Thorpe, TI vice president and manager of external development and manufacturing (EDM). "Working together, Amkor and TI rapidly developed, qualified and deployed a new package platform that will not only address TI's flip chip package needs for the next decade but will also serve as a game changer for the industry. This new packaging technology will drive down the size and cost of semiconductors while boosting performance - a win for TI, Amkor and our customers."

"Amkor and TI worked tirelessly to bring this complex technology to market against a challenging development timeline," said Ken Joyce, president and CEO of Amkor Technology. "Both organizations mobilized significant resources to advance the state of the art for copper pillar bumping, fine pitch interconnect assembly, and advanced packaging. We are committed to partnering with TI in applying this new technology on chip scale packages (CSP), conventional package on package (PoP), and next generation TMV PoP configurations."

Some of the key features of fine pitch flip chip with copper pillar technologies are:

1. Uses lead free technology. This technology acts as the platform interconnect technology for integration with silicon nodes.
2. The fine pitch flip chip layout design methodology typically reduces substrate layer count as compared to standard area array flip chip.
3. This package has a thin die, which, when combined with the low standoff height of the copper pillar bump itself, reduces package height.

Copper pillar flip chip packaging is an alternative solution in semiconductor packaging to get rid of the disadvantages of wirebond packaging at nodes of 45nm and below.

For more information visit: www.amkor.com, www.ti.com.