Date: 15/06/2010

Synopsys' Static Timing Analysis tool enhanced to handle 500 million instances

When the semiconductor node geometry goes below 90nm, the timing delay complexities in logic circuits gets compounded and it demands the Static Timing Analysis (STA) tools to handle more instances. To answer this requirement Synopsys has enhanced its STA tool Prime Time 2010 to handle 500 million instances. Synopsys says it has upgraged STA tool Prime Time to deliver 5 to 10 times more performace compared to its older version.

PrimeTime allows to do block-level timing analysis and allows to begin the timing closure process earlier in the chip design flow to drive timing closure in IC Compiler.

Antun Domic, senior vice president and general manager, Synopsys Implementation Group said "By adding HyperScale technology, the 2010.06 release of PrimeTime includes a significant innovation to extend STA scalability for the next five to 10 years".

To Know more visit www.synopsys.com