Date: 12/11/2009

Silicon Frontline's post-layout verification tool is validated by UMC and TSMC

Silicon Frontline Technology's post-layout verification tool F3D used in VLSI design is validated by UMC and TSMC for nanometer semiconductor design technologies. At the EDA event Design Automation Conference (DAC), Silicon Frontline was listed under top ten EDA techs EDA by market analysts.

"As we move toward 32nm technology, electronic designers need accurate design solutions that help them get to market quicker with high quality products," remarked Gary Smith, principal EDA analyst, GarySmithEDA. "The companies on our What To See @ DAC 2009 list represent EDA companies that offer new products in critical areas, like post-layout 3D extraction in the case of Silicon Frontline."