Date: 18/02/2010

Two-pin IEEE 1149.7 adopted by TI to test and debug SoCs

Texas Instruments has announced that it leads the adoption of new two-pin IEEE 1149.7 standard, which improves debug capabilities and power constraints for system-on-chip (SoC) architectures.

The key features of the IEEE 1149.7 standard are,

Provides a standard gateway to access other test and debug standards such as IEEE 1149.1, IEEE 1500 and IEEE P1687
Offers four selectable power modes to enable ultra-low power devices
Shorter scan chain lengths allows for fast debug operations and support for background data transfers concurrent with debug transactions

IEEE 1149.7 is complementary superset of the IEEE 1149.1 (JTAG) standard, which adds substantial functionality to the existing standard, but it is not a replacement for IEEE 1149.1. Backward compatibility is maintained so that any a board or system that integrates chips that support either standard is amenable to test or debug procedures.