Date: 04/11/2009

Low resistance tungsten metallization process for semiconductor chip manufacturing

Novellus has developed a new tungsten deposition process used in semiconductor chip manufacturing. The new process called LRWxT reduces contact and line resistance at the 3Xnm technology node up to 30% compared to conventional tungsten chemical vapor deposition (CVD-W) technology for memory and logic devices. The LRWxT enables optimal feature fill while reducing the resistivity of the deposited bulk tungsten layer.

LRWxT employs the high productivity, multi-station sequential architecture of the ALTUS Max CVD-W system to deliver a unique, three-step deposition process. First, a <20Å thick nucleation layer is deposited using Novellus' proprietary PNL®xT (Pulsed Nucleation Layer) technology. Next, a low-resistivity tungsten (LRWxT) treatment step is applied to promote growth of the low resistivity bulk film. Finally, an optimized CVD-W film is deposited for the bulk fill of nanometer-sized structures.

Novellus says, this new approach uses its ALTUS Max system for a unique deposition process sequence in high conformal, large grain size films with low tungsten bulk resistivity. The new process was developed and tested on device features provided by NEC Electronics, and the breakthrough was presented at this year's annual Advanced Metallization Conference in Baltimore.

"As semiconductor manufacturers advance to smaller technology nodes, minimizing the resistivity effects from device scaling is critical to improving electrical performance in logic and memory devices," said Dr. Patrick Lord, senior vice president for Novellus' Direct Metals, Surface Preparation, and Gapfill business units. "The ALTUS Max LRWxT process delivers industry-leading productivity to our customers while improving the speed and efficiency of their devices."

For more details visit www.novellus.com