Date: 26/01/2010

NEC Electronics adopts Cadence EDI system for 40-nm ASIC designs

NEC Electronics has adopted Cadence Encounter Digital Implementation (EDI) System for CB40L (40 nanometer low power) process technology ASIC designs.

EDI Systems' multi-threaded processing, netlist-to-netlist compilation, and integrated DFM optimization and timing signoff analysis, streamlined the high-density ASIC design processes.

EDI System also provides a complete, consistent, and converging flow to address design-for-manufacturing (DFM) and variability effects (lithography, CMP, thermal, and process variations) in the early stages of the design flow. By integrating model-based DFM and statistical technology in a prevention-analysis-repair flow, the Cadence solution is capable of handling high-density designs and provide high productivity gains over DFM-closure solutions.

"We are quite satisfied that the Cadence EDI System is fully capable of tackling our leading edge design challenges," said Akira Denda, Department Manager of the Device Platform Development Department, 1st SoC Business Planning Division at NEC Electronics ASIC Division. "EDI System enabled us to tapeout an area-efficient design while sustaining time-to-market by leveraging the end-to-end, multi-threaded solution."

"The Cadence EDI System provides significantly improved productivity and time-to-market, while reducing both the cost and risk associated with advanced semiconductor design," said Dr. Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. "The EDI System enabled NEC Electronics to tape-out its 40-nm ASIC designs, involving the incredibly complex integration of over 20 million gates in a single, low-power, area-efficient device. We're already lined up to execute additional advanced node designs with NEC Electronics, using EDI System with advanced node capabilities to reach fast, predictable design convergence."

For more details visit www.cadence.com, www.necel.com