Date: 11/01/2010

LSI achieves 25% overall leakage reduction by implementing TSMC's PowerTrim tech

LSI has achieved over 25% overall leakage reduction by implementing TSMC's PowerTrim power optimization technology on its 65nm low power (LP) process.

PowerTrim software analyzed the LSI design and substituted cells with small increases in gate length on non-critical timing paths. These small changes make a better impact by increasing gate length exponentially reduces leakage current.

The PowerTrim service is implemented in conjunction with other leakage reduction techniques such as multi-Vt cell libraries, reverse body biasing, header/footer sleep switches, and voltage islands. It provides additional leakage improvements and is more efficient in terms of leakage reduction per unit of slack than high-Vt transistors.

PowerTrim performs speed/power tradeoffs using a CD biasing technique that analyzes designs and applies gate length biases to the appropriate cells (i.e. non-critical paths possessing sufficient timing "slack"). The technology optimizes transistors along these paths without reducing chip performance. The gate CD biases are implemented as part of the Optical Proximity Correction (OPC) flow. The process does not impact cell footprint or chip area. The result is better leakage power reduction while maintaining chip performance and area. PowerTrim also reduces leakage power variability resulting in improved parametric yield.

"Low power consumption and high performance are key to the success of our products," said Norm Lawrence, director of Product and Test Engineering, Networking Components Division at LSI Corporation. "Working closely with TSMC and Tela Innovations, PowerTrim helped us reduce leakage power by over 25% while improving our yield distribution for leakage."

"Enabling our customers to improve important product features like power consumption is one of the key objectives of TSMC's Open Innovation Platform initiative," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. "Collaborating with innovative companies like Tela Innovations to provide an Open Innovation program creates differentiated value that is the central vision behind this initiative. We are quite pleased with the results that LSI achieved and are encouraged by their decision to deploy PowerTrim."

Availability: PowerTrim is available in 90nm, 80nm, 65nm, 55nm, and 40nm process nodes

For more details visit www.tsmc.com