Date: 06/06/2008

Indian Engineers severely lack exposure to semiconductor manufacturing

Though India boasts of fairly rich VLSI and Embedded talent, but it's engineering talent are least exposed to semiconductor fabrication. Even though there is lot of theory material available as part of the academic curriculum to design chips, there are no practical demonstrations and latest updated training material (explaining the 65nm process) available to educate students about the latest Integrated Circuit manufacturing technology in most of the engineering colleges India.

This is one of the reasons for students to opt for embedded line of career. In comparison to VLSI design, the embedded system design offers better scope for quick learning and fast growth. However in long-term basis, VLSI is a better career option.

Indian academia and the industry bodies got to play a joint role here to fill this vacuum in Indian Engineers and gear them up for the future surge in demand for VLSI design talent.

The easy way out for this is to, tie up with some of the fabs in US, EU and Taiwan to provide demonstration material (video presentation) and training on latest processes.
The recent good example is, ST Microelectronics, a leading Europe based semiconductor has tied up with Chinese universities, to provide them with design rules and design kits to design chips on 65nm process technologies. Through this tie-up, The Chinese universities can also get sample-customized chips manufactured at low cost. The link between universities and ST micro is not direct, it is through a broker named CMP (Circuit Multi Projects).

ST or any such leading semiconductor vendor are sure will be having same level interest to replicate this model with Indian universites.