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  Date: 19/01/2024

Creonic GmbH Introduces Advanced 5G LDPC Encoder IP core for Enhanced Mobile Broadband Connectivity

Creonic GmbH introduces the 5G LDPC Encoder IP core, a valuable addition to the diverse product portfolio, including field-proven 5G LDPC Decoders.

Designed with a focus on flexibility, the 5G LDPC Encoder features high throughput and low latency, aligning seamlessly with the standards set by 3GPP Release 15 for 5G LDPC encoding. Its applicability spans a wide spectrum, catering to the needs of 5G modem chipsets for base stations (BS) or user equipment (UE) and applications with the highest demands on error correction.

The encoder's high-throughput design ensures a performance of 5 Gbit/s on state-of-the-art FPGAs. In addition to speed, the encoder is highly efficient, ensuring a low-power and low-complexity design. The on-the-fly configuration allows for block-to-block adaptability, enhancing integration through AXI4-Stream handshaking interfaces for ASIC and FPGAs (AMD Xilinx, Intel).

The 5G LDPC Encoder IP core supports a wide range of applications with base code rates ranging from 22/68 to 22/26 for basegraph 1 and 10/52 to 10/14 for basegraph 2. It also includes puncturing, adding versatility to its functionality.

For additional details on the 5G LDPC Encoder and Decoder IP cores and Creonic's portfolio of communication IP cores, please visit our website.

Source: Creonic GmbH

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