Date: 15/09/2020

MIPI C-PHY/D-PHY Combo IP supports 30 Gbps

Mixel has announced the availability of MIPI C-PHYSM/D-PHYSM IP compliant with the MIPI C-PHY v2.0 and MIPI D-PHY v2.5 specifications. MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2SM) and Display Serial Interface (DSISM) and DSI-2SM. Mixel says this is the first IP where total aggregate speed reaches over 30 Gbps. MIPI C-PHY/D-PHY Combo IP supports 30 Gbps for high-performance imaging and display applications.

Mixel claims its MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer and can be configured as a MIPI transmitter or receiver, supporting both the camera interface CSI-2 v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification.

Mixel says its MIPI C-PHY v2.0 supports a speed of 4.5 Gsps per trio, an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18Gbps in their respective modes, as per Mixel.

Other features further shared by Mixel includes:
The Mixel MIPI C-PHY/D-PHY Combo IP includes many new features to both the D-PHY and C-PHY that was not available in previous versions of the specifications, namely Spread Spectrum Clocking (SSC), transmit equalization (de-emphasis), and receiver ISI calibration. It also supports new power saving functionality such as HS-TX reduced swing modes and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround that boosts transmission bandwidth in the reverse direction of the MIPI link. The ALP Mode is central to the CSI-2 Unified Serial Link feature that reduces number of interface wires and helps to natively support longer reach. The combo PHY IP not only shares the serial interface pins, but Mixel’s implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.

“As a longtime contributing member and early IP provider for MIPI D-PHY and MIPI C-PHY, Mixel has been a valued advocate for the advancement and adoption of MIPI PHYs for many years,” said Joel Huloux, MIPI Alliance chairman. “With its latest announcement, Mixel advances the capabilities of SoC designers with its flexible, higher bandwidth combo solution.”

“We are thrilled to provide our customers with another industry first,” said Ashraf Takla, President and CEO of Mixel. “We continue to demonstrate Mixel’s commitment to our customers by developing leading edge MIPI IP to meet our customers’ demand for higher bandwidth in advanced technologies.”