Date: 06/11/2012

STATS ChipPAC’s latest chip packaging supports 2.5 and 3D fabrication

STATS ChipPAC has expanded Wafer Level Ball Grid Array (eWLB) packaging options to include interposer technology, flip chip interconnect and complex 3D System-in-Package configuration of semiconductor ICs.

STATS ChipPAC explains the advancement of silicon scaling to 14 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities.

"We have taken the robust capabilities of eWLB and developed a solid integration platform for proven and successful 2.5D and 3D packaging integration. With our advanced eWLB technology we are able to provide our customers with the flexibility to integrate semiconductor die from diverse semiconductor processes and different silicon nodes into a cost effective interposer solution. We have also extended our eWLB capabilities into high-end flip chip Ball Grid Array (fcBGA) packaging to address future technical challenges in flip chip assembly as advanced technology nodes move below 28nm," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

"We are leveraging our eWLB technology to drive substrate simplification and cost reduction while achieving tighter line/spaces in a range of 2.5D to 3D configurations that deliver product advantages to our customers in terms of higher performance, higher frequencies, higher bandwidth and thinner package profiles. With eWLB we have the flexibility to embed multiple active and passive components in the same wafer level package with a vertical 3D interconnection that can be achieved without the use of TSV," said Dr. Han.